verilog HDL module traffic_lights/*(on,off,red_tics,amber_tics,green_tics,clock,red,amber,green)*/;\x05/*input on,off,red_tics,amber_tics,green_tics;\x05output clock,red,amber,green;\x05wire red_tics,amber_tics,green_tics;*/\x05reg clock,red,amber,gr

来源:学生作业帮助网 编辑:作业帮 时间:2024/05/10 20:23:08
verilog HDL module traffic_lights/*(on,off,red_tics,amber_tics,green_tics,clock,red,amber,green)*/;\x05/*input on,off,red_tics,amber_tics,green_tics;\x05output clock,red,amber,green;\x05wire red_tics,amber_tics,green_tics;*/\x05reg clock,red,amber,gr

verilog HDL module traffic_lights/*(on,off,red_tics,amber_tics,green_tics,clock,red,amber,green)*/;\x05/*input on,off,red_tics,amber_tics,green_tics;\x05output clock,red,amber,green;\x05wire red_tics,amber_tics,green_tics;*/\x05reg clock,red,amber,gr
verilog HDL
module traffic_lights/*(on,off,red_tics,amber_tics,green_tics,clock,red,amber,green)*/;
\x05/*input on,off,red_tics,amber_tics,green_tics;
\x05output clock,red,amber,green;
\x05wire red_tics,amber_tics,green_tics;*/
\x05reg clock,red,amber,green;
\x05parameter on=1,off=0,red_tics=350,amber_tics=30,green_tics=200;
\x05initial red=off;
\x05initial amber=off;
\x05initial green=off;
\x05
\x05always
\x05begin
\x05\x05red=on;
\x05\x05light(red,red_tics);
\x05\x05green=on;
\x05\x05light(green,green_tics);
\x05\x05amber=on;
\x05\x05light(amber,amber_tics);
\x05end
\x05
\x05task light;
\x05\x05output color;
\x05\x05input [31:0] tics;
\x05begin
\x05\x05repeat(tics)@(posedge clock)
\x05\x05\x05color=off;
\x05end
\x05endtask
\x05
\x05
\x05always
\x05\x05begin
\x05\x05
\x05\x05#100 clock=0;
\x05\x05#100 clock=1;
\x05\x05end
\x05\x05
endmodule
以上是一个红绿黄交通灯行为模块,
我现在想调用这个模块应该怎么调用啊,怎么确定他的输入输出端口,我想像我注释里面那样综合成原理图,可是出现了错误,本人verilog HDL新手.

verilog HDL module traffic_lights/*(on,off,red_tics,amber_tics,green_tics,clock,red,amber,green)*/;\x05/*input on,off,red_tics,amber_tics,green_tics;\x05output clock,red,amber,green;\x05wire red_tics,amber_tics,green_tics;*/\x05reg clock,red,amber,gr
%是取模,就是余数,/是算商数.
signed constant关键在于计算顺序,和2补码.举例说第一个式子应该是
(-(4‘d12))%3.= (-(4’b1100))%3= 4'b100%3=1
第二个4’sd12=-4,-4‘sd12=-(-4)=4
第三个'sd12=32'd12,不写位数认为是32bit.